Integrated circuit designs that incorporate trim circuits to adjust critical parameters with high precision conventionally require 100 percent test and trim. This is an expensive and time-consuming process.
FIG. 1 illustrates a generic, conventional probe and trim test procedure typically used for a trim adjustable integrated circuit. Normally, such a device is measured prior to trimming, target values are calculated, and a trim routine is executed to adjust a specific parameter to a desired value on every die. Reviewing FIG. 1, a pre-trim measurement is made and then it is determined if the trim parameter is inside the trim capability. If not inside the trim capability the chip is deemed a failure and is sorted to the appropriate failure category. The system records this on the wafer map and then goes or indexes to the next chip. If measurements are within the trim capability then the trim routine is executed. After trim routine execution, the next step is to measure the next parameter and determine if the next parameter passes specification. If not the chip is sorted to a failure bin, the wafer map is updated, and the system moves to the next chip. This step is repeated until all successive parametric test specifications have been measured. If all specification requirements are met the chip is deemed good, the wafer map is updated accordingly, and the system having determined that all tests have been successfully completed proceeds to the next chip.